The present invention relates generally to a process for improving gallium arsenide field effect transistor performance using an aluminum arsenide or an aluminum gallium arsenide barrier layer.
The following papers are of interest.
(1) S. Swirhun, S. Hanka, J. Nohava, D. Grider, and P. Bauhahn, "Refractory self-aligned-gate, GaAs FET based circuit technology for high ambient temperatures", Proceedings of First International High Temperature Electronics Conference, pp. 295-300, 1991. PA1 (2) K. Fricke, H. L. Hartnagel, R. Schutz, G. Schweeger, and J. Wurfl, "A new GaAs technology for stable FET's at 300.degree. C.", IEEE Electron Dev. Lett., vol. 10, no. 12, pp 577-579, 1989. PA1 U.S. Pat. No. 5,300,795, - Saunier et al
S. Swirhun et al at Honeywell have tested FETs fabricated with a self-aligned gate(SAG) process, using dopant implants, isolation implants, tungsten silicide (Wsi) Schottky gates, NiGeNiInNiMo ohmic metal contacts, and SiN passivation. For a 1.1.times.10 .mu.m FET, a drain current on-to-off ratio of about 30:1 was obtained at 350.degree. C. ambient temperature.
K. Fricke et al from West Germany have fabricated FETs grown by metal-organic chemical vapor deposition (MOCVD) using TiPtAu Schottky gates GeAuNiWSiTiWSiAu ohmic contacts, and SiN passivation. Their device test results are difficult to interpret because the results are shown at estimated temperature and not at the measured ambient temperature. In both cases, however, the switching current ratios were inferior by at least an order of magnitude to FETs fabricated with the AlAs buffer layer.
The following United States patents is of interest.